Toward architecture-based test-vector generation for timing verification of fast parallel multipliers

Authors:
Henrik Eriksson;Per Larsson-Edefors;Daniel Eckerbert
Affiliations:
SP--Swedish National Testing and Research Institute, Boras, Sweden and VLSI Research Group, Department of Computer Science and Engineering, Chalmers University of Technology, Gothenburg, Sweden;VLSI Research Group, Department of Computer Science and Engineering, Chalmers University of Technology, Gothenburg, Sweden;IMEGO--the Institute of Microelectronics, Gothenburg, Sweden and VLSI Research Group, Department of Computer Science and Engineering, Chalmers University of Technology, Gothenburg, Sweden
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2006

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Abstract

Fast parallel multipliers that contain logarithmic partial-product reduction trees pose a challenge to simulation-based high-accuracy timing verification, since the reduction tree has many reconvergent signal branches. However, such a multiplier architecture also offers a clue as how to attack the test-vector generation problem. The timing-critical paths are intimately associated with long carry propagation. We introduce a multiplier test-vector generation method that has the ability to exercise such long carry propagation paths. Through extensive circuit simulation and static timing analysis, we evaluate the quality of the test vectors that result from the new method. Especially for fast multipliers with a pronounced carry propagation, the timing-critical vectors manage to stimulate a path, which has a delay that comes close to the true worst case delay. We investigate the complexity and run-time for the test-vector generation, and derive timing-critical vectors up to a factor word length of 54 bits.