Practical programming in Tcl and Tk (3rd ed.)
Practical programming in Tcl and Tk (3rd ed.)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
NIM: a noise index model to estimate delay discrepancies between silicon and simulation
Proceedings of the Conference on Design, Automation and Test in Europe
Enabling system-level modeling of variation-induced faults in networks-on-chips
Proceedings of the 48th Design Automation Conference
Current source modeling for power and timing analysis at different supply voltages
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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At sign-off everybody is wondering about how good the accuracy of the static timing analysis timing reports generated with PrimeTime炉 really is. Errors can be introduced by STA setup, interconnect modeling, library characterization etc. The claims that path timingcalculated by PrimeTime usually is within a few percent of Spice don't help to ease your uncertainty.When the Signal Integrity features were introduced to PrimeTime there was also a feature added that was hardly announced: PrimeTime can write out timing paths for simulation with Spice that can be used to validate the timing numbers calculated by PrimeTime. By comparingthe numbers calculated by PrimeTime to a simulation with Spice for selected paths the designers can verify the timing and build up confidence or identify errors.This paper will describe a validation flow for PrimeTime timing reports that is based on extraction of the Spice paths, starting the Spice simulation, parsing the simulation results, and creating a report comparing PrimeTime and Spice timing. All these steps are done inside the TCL environment of PrimeTime. It will describe this flow, what is needed for the Spice simulation, how it can be set up, what can go wrong, and what kind of problems in the STA can be identified.