High-level algorithm and architecture transformations for DSP synthesis
Journal of VLSI Signal Processing Systems - Special issue on design environments for DSP
A specification invariant technique for operation cost minimisation in flow-graphs
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Optimal Circuits for Parallel Multipliers
IEEE Transactions on Computers
An Optimal Allocation of Carry-Save-Adders in Arithmetic Circuits
IEEE Transactions on Computers
Signal representation guided synthesis using carry-save adders for synchronous data-path circuits
Proceedings of the 38th annual Design Automation Conference
Improved merging of datapath operators using information content and required precision analysis
Proceedings of the 38th annual Design Automation Conference
Computer Arithmetic I (Tutorial)
Computer Arithmetic I (Tutorial)
Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
Leakage power minimization for the synthesis of parallel multiplier circuits
Proceedings of the 14th ACM Great Lakes symposium on VLSI
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In deep submicron (DSM) design, the interconnect delay becomes equally as or more important than that of logic gates. In particular, to achieve timing closure in DSM design, it is essential to consider the interconnect delay at an early stage of the synthesis process. Unfortunately, few successes of achieving a tight link of front-end synthesis to back-end layout have been reported, in a practical point of view, mainly due to the inaccuracy of predicting the layout effects during the synthesis. In this paper, we address a new approach that refines the structure and placement of the circuit by iteratively performing the two tasks, Timing-driven replacement and Timing-driven resynthesis. The iterative mechanism of the two tasks practically tightly integrates the synthesis and placement tasks so that both of the effects of placement on the results of synthesis and the effects of synthesis on the results of placement are fully and effectively taken into account. From experiments using a set of benchmark designs, it is shown that the approach is quite effective, and efficient, producing designs with 6.6%-21.4% shorter timing over the conventional method.