Semi-Logarithmic Number Systems
IEEE Transactions on Computers
Optimal Circuits for Parallel Multipliers
IEEE Transactions on Computers
New Minimal Modified Radix-r Representation with Applications to Smart Cards
PKC '02 Proceedings of the 5th International Workshop on Practice and Theory in Public Key Cryptosystems: Public Key Cryptography
High-Radix Design of a Scalable Modular Multiplier
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
A Fast Optimal Robust Path Delay Fault Testable Adder
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Svoboda-Tung division with no compensation
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
(Quasi-) Linear Path Delay Fault Tests for Adders
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
An integrated approach to timing-driven synthesis and placement of arithmetic circuits
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Encyclopedia of Computer Science
Efficient implementation of constant coefficient division under quantization constraints
ICC'05 Proceedings of the 9th International Conference on Circuits
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