Dependability evaluation of time-redundancy techniques in integer multipliers

Authors:
Henrik Eriksson
Affiliations:
SP Technical Research Institute of Sweden, Borås, Sweden
Venue:
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Year:
2007

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Abstract

An evaluation of the fault tolerance which can be achieved by the use of time-redundancy techniques in integer multipliers has been conducted. The evaluated techniques are: swapped inputs, inverted reduction tree, a novel use of the half precision mode in a twin-precision multiplier, and a combination of the first two techniques. The faults which have been injected are single stuck-atzero or stuck-at-one faults. Error detection coverage has been the evaluation criteria. Depending on the technique, the attained error detection coverage spans from 25% to 90%.