Dependability evaluation of time-redundancy techniques in integer multipliers
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
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This paper proposes a design of a defect tolerant Wallace multipliers. A repair procedure for the pro-posed design i s also shown. T h i s paper evaluates t h e proposed design from the view point of t h e yield, area and delay time. For example, the yield of a 32 x 32 Wallace multiplier increases from 0.90 t o 0.99 by applying the proposed design while the area increases by a factor of 1.39.