Novel Fault-Tolerant Adder Design for FPGA-Based Systems

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IOLTW '01 Proceedings of the Seventh International On-Line Testing Workshop
Year:
2001

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Abstract

Abstract: In this paper we propose a novel fault-tolerant adder which is suitable to be used for highly dependable systems implemented by means of Field-Programmable Gate Arrays (FPGAs). Compared to alternate conventional designs, the one presented here allows to achieve fault-tolerance at lower design costs. A prototype has been developed, whose expected behavior has been verified by means of post-layout simulations and experimental measurements. Although our adder has been conceived for FPGA-based systems, it is also suitable to be implemented by means of VLSI and very deep sub-micron technologies.