An Efficient Twin-Precision Multiplier

Authors:
Magnus Sjalander;Henrik Eriksson;Per Larsson-Edefors
Affiliations:
Chalmers University of Technology, Sweden;Chalmers University of Technology, Sweden;Chalmers University of Technology, Sweden
Venue:
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Year:
2004

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Abstract

We present a twin-precision multiplier that in normal operation mode efficiently performs N-b multiplications. For applications where the demand on precision is relaxed, the multiplier can perform N/2-b multiplications while expending only a fraction of the energy of a conventional N-b multiplier. For applications with high demands on throughput, the multiplier is capable of performing two independent N/2-b multiplications in parallel. A comparison between two signed 16-b multipliers, where both perform single 8-b multiplications, shows that the twin-precision multiplier has 72% lower power dissipation and 15% higher speed than the conventional one, while only requiring 8% more transistors.