High performance motion estimation architecture using efficient adder-compressors

Authors:
André Silva;Eduardo Costa;Sergio Almeida;Marcelo Porto;Sergio Bampi
Affiliations:
Universidade Católica de Pelotas, Pelotas, Brazil;Universidade Católica de Pelotas, Pelotas, Brazil;Universidade Católica de Pelotas, Pelotas, Brazil;Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil;Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil
Venue:
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
Year:
2009

Citing 4
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Abstract

This paper presents a high performance architecture for motion estimation (ME) using efficient adder compressors. The architecture is based on the Quarter Sub-sampled Diamond Search algorithm (QSDS) with Dynamic Iteration Control (DIC) algorithm. The main characteristic of the proposed architecture is the large amount of processing units (PUs) that are used to calculate the SAD (Sum of Absolute Differences) metric. The internal structures of the PUs are composed by a large number of addition operations to calculate the SADs. In this paper, efficient 4-2 and 8-2 adder compressors are used in the PUs architecture to achieve a higher performance. These adder compressors enable the simultaneous addition of 4 and 8 operands respectively. The PUs, using adder compressors, were applied to the ME architecture. The implemented architectures were described in VHDL and syntethized with Leonardo Spectrum tool to the TSMC 0.18μm CMOS standard cell technology. Synthesis results indicate that the new QSDS-DIC architectures reach the best performance result and enable gains of 12% in terms of processing rate. The architectures can reach real time for HDTV (1920x1080 pixels) in the worst case processing 65 frames per second, and they can process 269 HDTV frames per second in the average case.