Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation
Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation
A novel configurable motion estimation architecture for high-efficiency MPEG-4/H.264 encoding
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
High performance motion estimation architecture using efficient adder-compressors
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
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This paper presents a high throughput and low hardware cost architecture for motion estimation (ME) using a Quarter Subsampled Diamond Search algorithm (QSDS) with Dynamic Iteration Control (DIC). QSDS-DIC is a new algorithm proposed in this paper, which was developed to focus an efficient hardware design of ME. QSDS-DIC is based on the well known Diamond Search algorithm (DS) and on the sub-sampling technique. Besides this, DIC was developed to allow better synchronization and quality. A software evaluation presents the average results for quality and computational cost of QSDS, QSDS-DIC, Full Search and DS block matching algorithms. The designed hardware architecture considered blocks with 16x16 samples. The architecture was described in VHDL and mapped to a Xilinx Virtex-4 FPGA and to TSMC 0.18¼m CMOS standard cells. Synthesis results for FPGA indicate that QSDS-DIC architecture is able to run at 213.3 MHz, while taking only 3610 LUTs. This architecture can reach real time for HDTV (1920x1080 pixels) in the worst case, and it can process 188 HDTV frames per second in the average case.