The design and analysis of VLSI circuits
The design and analysis of VLSI circuits
Algorithms for Iterative Array Multiplication
IEEE Transactions on Computers
Introduction to VLSI Systems
Single-Precision Multiplier with Reduced Circuit Complexity for Signal Processing Applications
IEEE Transactions on Computers
Multiplexer-Based Array Multipliers
IEEE Transactions on Computers
An RNS Architecture for Quasi-Chaotic Oscillators
Journal of VLSI Signal Processing Systems
Fast Combinatorial RNS Processors for DSP Applications
IEEE Transactions on Computers
A New Design Technique for Column Compression Multipliers
IEEE Transactions on Computers
A high-speed radix-4 multiplexer-based array multiplier
Proceedings of the 18th ACM Great Lakes symposium on VLSI
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A parallel multiplier design based on the five-counter cell is discussed. A design optimization for the performance in speed is proposed at the logic design level which is developed into an MOS circuit design. The comparison of the five-counter cell design and the full adder cell design reveals that the proposed design is most useful with pass gate logic and results in high-speed multiplication (approximately twice as fast as that of the full adder design) with a moderate increase in hardware complexity. With the five-counter design, an improvement in the hardware complexity of a squarer can be expected.