Pipelined area-efficient digit serial divider

  • Authors:

  • A. E. Bashagha

  • Affiliations:

  • School of Engineering & Technology, Faculty of Computing Sciences and Engineering, De Montfort University, Leicester LE1 9BH, UK

  • Venue:
  • Signal Processing
  • Year:
  • 2003

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Abstract

In this paper, a new two's complement radix-2n area-efficient digit serial divider is presented. The proposed digit serial divider is designed by cascading N (wordlength) digital controlled add/subtract DCAS cells where each cell is used to generate one of the N quotient bits. Two types of the DCAS cells namely a carry select controlled add/subtract CSCAS cell and a carry generate controlled add/subtract CGCAS are proposed. The new DCAS cells can be fully pipelined to the bit level using only one set of cuts. The proposed pipelined divider could achieve the same throughput rate as the existing ones by using nearly half the number of pipelining levels. As a result, it requires less silicon area and it has less initial delay. The new digit serial divider is based on radix-2n arithmetic and therefore, it is simple and general for any digit size, n. Any adder can be used to perform the n-bit addition of the DCAS cells.