Computer number systems and arithmetic
Computer number systems and arithmetic
Design of a high-speed square root multiply and divide unit
IEEE Transactions on Computers
Computer methods for engineering
Computer methods for engineering
Digital Computer Arithmetic
Real-time display of quadric on the I.M.O.G.E.N.E. machine
SMA '91 Proceedings of the first ACM symposium on Solid modeling foundations and CAD/CAM applications
Higher Radix Square Root with Prescaling
IEEE Transactions on Computers - Special issue on computer arithmetic
Proceedings of the 1999 ACM symposium on Applied computing
Proceedings of the 8th IMA International Conference on Cryptography and Coding
A 33MHz 16-bit gradient calculator for real-time volume imaging
EGGH'94 Proceedings of the Ninth Eurographics conference on Graphics Hardware
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An algorithm for evaluating the square root of integers and real numbers is developed. The procedure consists of two parts: one to obtain a close estimate of the square root and the other to modify the initial value, iteratively, until a precise root is evaluated. The major effort in this development has been concentrated on two objectives: high speed and no division operation other than division by 2. The first objective is achieved through a simple two-step procedure for getting the first estimate, and then modifying it by employing a fast converging iteration technique. The second objective is also fulfilled through applying bit-shift operation rather than division operation. The algorithm is simulated for both integer and real numbers, and the results are compared to two methods being widely used. The results (tabulated) show considerable improvement in speed compared to these other two methods.