Computer number systems and arithmetic
Computer number systems and arithmetic
The fast Fourier transform and its applications
The fast Fourier transform and its applications
Spare Capacity as a Means of Fault Detection and Diagnosis in Multiprocessor Systems
IEEE Transactions on Computers
Householder reduction of linear equations
ACM Computing Surveys (CSUR)
Digital Computer Arithmetic
The Test Access Port and Boundary-Scan Architecture
The Test Access Port and Boundary-Scan Architecture
IEEE Design & Test
From Specification Validation to Hardware Testing: A Unified Method
Proceedings of the IEEE International Test Conference on Test and Design Validity
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This paper presents a unified approachwhich allows efficient concurrent tests to beconsidered when synthesizing scalable signalprocessing multiprocessor architectures. Theapproach is based on two earlier works. Thefirst work has allowed the synthesis of scalablemultiprocessor architectures where comparisontesting is considered. The second work hasshown the feasibility of using a softwaretechnique called Mutation testing tosuccessfully test hardware devices. Thepresented approach ensures that VLSI digitalsignal processors (DSP) are totally testedconcurrently within useful computation. Basedon realistic examples of signal processingapplications and state-of-the-art DSPs, theapproach is shown highly efficient in terms offault coverage and fault latency.