FPGA implementation of variable-precision floating-point arithmetic

Authors:
Yuanwu Lei;Yong Dou;Song Guo;Jie Zhou
Affiliations:
Department of Computer Science, National University of Defence Technology, Changsha, P.R. China;Department of Computer Science, National University of Defence Technology, Changsha, P.R. China;Department of Computer Science, National University of Defence Technology, Changsha, P.R. China;Department of Computer Science, National University of Defence Technology, Changsha, P.R. China
Venue:
APPT'11 Proceedings of the 9th international conference on Advanced parallel processing technologies
Year:
2011

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Abstract

This paper explores the capability of FPGA solutions to accelerate scientific applications with variable-precision floating-point (VP) arithmetic. First, we present a special-purpose Very Large Instruction Word (VLIW) architecture for VP arithmetic (VV-Processor) on FPGA, which uses unified hardware structure to implement various VP algebraic and transcendental functions. We take exponential and trigonometric functions (sine and cosine) as examples to illustrate the design of VP elementary algorithms in VV-Processor, where the optimal configuration is discussed in details in order to achieve minimum execution time. Finally, we create a prototype of VV-Processor unit and Boost Accelerator based-on VV-Processor into a Xilinx Virtex-6 XC6VLX760- 2FF1760 FPGA chip. The experimental results show that our design, based on FPGA running at 253 MHz, outperforms the approach of a software-based library running on an Intel Core i3 530 CPU at 2.93GHz by a factor of 5-37X. Compared to the previous work, our design has higher performance and more flexibility to implement other VP elementary functions.