Hardware Design and Arithmetic Algorithms for a Variable-Precision, Interval Arithmetic Coprocessor

Authors:
Michael J. Schulte;Earl E. Swartzlander, Jr.
Affiliations:
-;-
Venue:
ARITH '95 Proceedings of the 12th Symposium on Computer Arithmetic
Year:
1995

Citing 0
Cited 5

Low-power behavioral synthesis optimization using multiple precision arithmetic

Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A Family of Variable-Precision Interval Arithmetic Processors

IEEE Transactions on Computers
CORDIC Processor for Variable-Precision Interval Arithmetic

Journal of VLSI Signal Processing Systems
FPGA implementation of variable-precision floating-point arithmetic

APPT'11 Proceedings of the 9th international conference on Advanced parallel processing technologies
FPGA implementation of an exact dot product and its application in variable-precision floating-point arithmetic

The Journal of Supercomputing

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents the hardware design and arithmetic algorithms for a coprocessor that performs variable-precision, interval arithmetic. The coprocessor gives the programmer the ability to specify the precision of the computation, determine the accuracy of the results, and recompute inaccurate results with higher precision. Direct hardware support and efficient arithmetic algorithms for variable-precision, interval arithmetic greatly improve the speed, accuracy and reliability of numerical computations Performance estimates indicate that the coprocessor is 200 to 1,000 times faster than a software package for variable-precision, interval arithmetic. The coprocessor can be implemented on a single chip with a cycle time that is comparable to IEEE double-precision floating point coprocessors.