Dynamic Precision Management for Loop Computations on Reconfigurable Architectures
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
BigSky-An On-Line Arithmetic Design Tool for FPGAs
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Microprocessors & Microsystems
FPGA implementation of variable-precision floating-point arithmetic
APPT'11 Proceedings of the 9th international conference on Advanced parallel processing technologies
The Journal of Supercomputing
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This paper presents the organization of an arithmetic unit for variable long-precision (VLP) operands suitable for reconfigurable computing. The reconfigurable arithmetic coprocessor (RAC) cooperates with the host computer in the VLP tasks. The main design issues addressed in the paper are: (a) mapping of the most frequent and time consuming operations of the VLP arithmetic algorithms to RAC, and (b) design of VLP algorithms that allow reduced reconfiguration time between arithmetic operations. The VLP arithmetic algorithms proposed cover multiplication, division and square root. In this paper we present the main building blocks used in the VLP arithmetic circuits, show the similarities of each arithmetic operator and present area/time estimates of these circuits in Xilinx FPGAs.KEYWORD_LIST: long-precision, computer arithmetic, reconfigurable architecture