A novel design of a two operand normalization circuit

  • Authors:

  • Elisardo Antelo;Montserrat Bóo;Javier D. Bruguera;Emilio L. Zapata

  • Affiliations:

  • Department Electrónica e Computación of the University of Santiago de Compostela, Santiago de Compostela, Spain;Department Electrónica e Computación of the University of Santiago de Compostela, Santiago de Compostela, Spain;Department Electrónica e Computación of the University of Santiago de Compostela, Santiago de Compostela, Spain;Department Arquitectura de Computadores, University of Málaga, Málaga, Spain

  • Venue:
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • Year:
  • 1998

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Abstract

This paper presents a new design for two operand normalization. The two operand normalization operation involves the normalization of at least one of two operands by left shifting both by the same amount. Our design performs the computation of the shift by making an OR of the bits of both operands in a tree network, encoding the position of the first nonzero bit. The encoded position is obtained most significant bit first, and then there is an overlapping with the shifting operation. The design we propose replaces two leading zero detector circuits and a comparator, that are present in the conventional approach. Our scheme demonstrates to be more area efficient than the conventional one. The circuit we propose is useful in floating point complex multiplication and COordinate Rotation DIgital Computer (CORDIC) processors.