A power modeling and characterization method for the CMOS standard cell library

  • Authors:

  • Jiing-Yuan Lin;Wen-Zen Shen;Jing-Yang Jou

  • Affiliations:

  • Department of Electronics Engineering & Institute of Electronics, National Chiao Tung University, HsinChu 30050, Taiwan, R.O.C.;Department of Electronics Engineering & Institute of Electronics, National Chiao Tung University, HsinChu 30050, Taiwan, R.O.C.;Department of Electronics Engineering & Institute of Electronics, National Chiao Tung University, HsinChu 30050, Taiwan, R.O.C.

  • Venue:
  • Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
  • Year:
  • 1997

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Abstract

In this paper, we propose power consumption models for complex gates and transmission gates, which are extended from the model of basic gates proposed in [1]. We also describe an accurate power characterization method for CMOS standard cell libraries which accounts for the effects of input slew rate, output loading, and logic state dependencies. The characterization methodology separates the power consumption of a cell into three components, e.g., capacitive feedthrough power, short-circuit power, and dynamic power. For each component, power equation is derived from SPICE simulation results where the netlist is extracted from cell's layout. Experimental results on a set of ISCAS'85 benchmark circuits show that the power estimation based on our power modeling and characterization provides within 7% error of SPICE simulation on average while the CPU time consumed is more than two orders of magnitude less.