Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Reducing power dissipation after technology mapping by structural transformations
DAC '96 Proceedings of the 33rd annual Design Automation Conference
An exact gate decomposition algorithm for low-power technology mapping
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Layout techniques supporting the use of dual supply voltages for cell-based designs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A practical gate resizing technique considering glitch reduction for low power design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Data driven power optimization of sequential circuits
Proceedings of the conference on Design, automation and test in Europe
Register transfer level power optimization with emphasis on glitch analysis and reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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1bit full adders and counters are usually used as basic cells in the arithmetic circuits. Characteristics of these components have strong impact on power, delay, and area of the arithmetic circuits. In this paper we propose a design method for low power arithmetic circuits, which the designer selects basic cells from a set of circuits with different structures(symmetrical one and asymmetrical one) by the method and the mothod optimizes connections to the terminals of the basic cells. Experimental results demonstrate 32.1% power reduction of a parallel multiplier designed by the proposed technique.