Variable input delay CMOS logic for low power design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of variable input delay gates for low dynamic power circuits
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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For correct functioning of CMOS circuits, every gate in the circuit needs to have an output transition, at most once for every input change. But in reality, the gates transition more than once due to unequal arrival times of signals at their inputs. These extra transitions are called glitches and they consume power. The dynamic power due to glitches in a CMOS circuit, can be eliminated by the introduction of delay buffers at specific nets but some extra power would be consumed by these buffers. In this thesis we propose a new methodology of eliminating the glitches without the insertion of delay buffers. The glitches are suppressed by the manipulation of the input delay of gates creating different delays for different input-output paths within the same gate. The technology constraints for the feasible ranges for length and width of transistors restrict the obtainable I/O delay difference for a gate. This difference is specified by an upper bound ub in the thesis. A given value of ub would result in a minimum dynamic power design that is the fastest allowed by that technology. The circuit is designed by a linear program (LP) that determines the component delays to eliminate all glitches. We do not pose the problem as the conventional transistor sizing because delays are non-linearly related to transistor size parameters. We propose to solve the problem in three phases. The first phase is a detailed study of a single gate to determine the allowed ub for the technology. In the second phase, an LP of size proportional to the circuit size is formulated by treating the gate level input delay variables independent of each other, but constrained by ub. We describe this as variable input delay logic design in the thesis. The third phase consists of the design of gates according to the delay assignment solution of the LP. Hence, the non-linearity in transistor sizing is relegated to the third phase, leaving the variables in the second phase independent. We describe possible ways of implementing the variable input delay logic at the transistor level. The gates can be designed by either input capacitance manipulation or by inserting resistances at gate inputs by inserting pass transistors. This technique is scalable to large circuits because the formulation is linear. The circuits designed by this method are totally glitch-free and may use a minimal number of delay buffers necessary to satisfy the input-output delay specification. Our design of the benchmark circuit c7552 containing 3827 gates achieved a peak power savings of 68% and an average energy saving of 58% compared to an unoptimized circuit having the same input-output delay specification. This optimized circuit consumed 18% less energy than the circuit designed by inserting buffers at the same delay specification.