Introduction to algorithms
Transition density, a stochastic measure of activity in digital circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Performance enhancement of CMOS VLSI circuits by transistor reordering
DAC '93 Proceedings of the 30th international Design Automation Conference
Transistor reordering rules for power reduction in CMOS gates
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
Reducing Power Dissipation in Serially Connected MOSFET Circuits via Transistor Reordering
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Minimizing power consumption of static CMOS circuits by transistor sizing and input reordering
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Lowering power consumption in concurrent checkers via input ordering
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Gate oxide leakage and delay tradeoffs for dual-toxcircuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of variable input delay gates for low dynamic power circuits
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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This paper addresses the optimization of a circuit for low power using transistor reordering. The optimization algorithm relies on a stochastic model of a static CMOS gate that includes the power of internal nodes of the gate. This power-consumption model depends on the switching activity and the equilibrium probabilities of the inputs of the gate. The model allows an exploration of the different configurations of a gate that are obtained by reordering its transistors. Thus, the best configuration of each gate is selected and the overall power consumption of the circuit is reduced.