PERFLEX: a performance driven module generator
EURO-DAC '92 Proceedings of the conference on European design automation
Performance enhancement of CMOS VLSI circuits by transistor reordering
DAC '93 Proceedings of the 30th international Design Automation Conference
Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Optimizing CMOS Circuits for Low Power Using Transistor Reordering
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
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In this paper we present new techniques to reduce the power consumption of a static CMOS circuit by enlarging transistors in high fan-out gates and reordering inputs to the gates. The techniques are developed based on observations from results of hspice simulations. These methods are incorporated into a performance and power constrained module generator, PowerSizer. Experimental results from the module generator on several real circuits show that as much as 15% saving in power consumption can be obtained on arithmetic circuits with almost no tradeoff in area or delay.