Device-circuit optimization for minimal energy and power consumption in CMOS random logic networks

  • Authors:
  • Pankaj Pant;Vivek De;Abhijit Chatterjee

  • Affiliations:
  • Georgia Institute of Technology;Intel Corp., Hillsboro, OR;Georgia Institute of Technology

  • Venue:
  • DAC '97 Proceedings of the 34th annual Design Automation Conference
  • Year:
  • 1997

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Abstract

We demonstrate a new approach minimizing the total ofthe static and the dynamic power dissipation components in aCMOS logic network required to operate at a specified clockfrequency using joint optimization of both device and circuitdesigns for a specific logic schematic and activity profile.We present a new approach to designing ultra low-powerCMOS logic circuits by joint optimization of supply voltage,threshold voltage and device widths for a specified speedconstraints.The static (leakage) and dynamic (switching)energy components are considered and an efficient heuristicis developed that delivers over an order of magnitude savingsin power over conventional optimization methods.