Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Static power optimization of deep submicron CMOS circuits for dual VT technology
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
VTCMOS characteristics and its optimum conditions predicted by a compact analytical model
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Variable threshold CMOS (VTCMOS) in series connected circuits
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Algebric Decision Diagrams and Their Applications
Formal Methods in System Design
A predictably low-leakage ASIC design style
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Fast Probability-Based Algorithm for Leakage Current Reduction Considering Controller Cost
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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In this paper we introduce a low-leakage standard cell based ASIC design methodology which is based on the use of modified standard cells. These cells are designed to consume extremely low and predictable leakage currents in standby mode. For each cell in a standard cell library, we design two low-leakage variants of the cell. If the inputs of a cell during the standby mode of operation are such that the output has a high value, we minimize the leakage in the pull-down network, and vice versa. While technology mapping a circuit, we determine the particular variant to utilize in each instance, so as to minimize leakage of the final mapped design.We have designed and laid out our modified standard cells, and have performed experiments to compare placed-and-routed area, leakage and delays of our method against MTCMOS and a straightforward ASIC flow. Each design style we compare utilizes the same base standard cell library.Our results show that designs obtained using our methodology have better speed and area characteristics than designs implemented in MTCMOS. The exact leakage current obtained for MTCMOS is highly unpredictable, while our method exhibits leakage currents which are precisely estimable. The leakage current for HL designs can be dramatically lower than the worst-case leakage of MTCMOS based designs, and two orders of magnitude compared to traditional standard cells. Also, a design implemented in MTCMOS would require the use of separate power and ground supplies for latches and combinational logic, while our methodology does away with such a requirement.