An ASIC design methodology with predictably low leakage, using leakage-immune standard cells
Proceedings of the 2003 international symposium on Low power electronics and design
VTCMOS characteristics and its optimum conditions predicted by a compact analytical model
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
A predictably low-leakage ASIC design style
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low power and high performance sram design using bank-based selective forward body bias
Proceedings of the 19th ACM Great Lakes symposium on VLSI
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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