Proceedings of the 2004 Asia and South Pacific Design Automation Conference
An efficient surface-based low-power buffer insertion algorithm
Proceedings of the 2005 international symposium on Physical design
Proceedings of the 42nd annual Design Automation Conference
Improving run times by pruned application of synthesis transforms
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Digital Circuit Optimization via Geometric Programming
Operations Research
An efficient low-power buffer insertion with time and area constraints
ICC'10 Proceedings of the 14th WSEAS international conference on Circuits
POMR: a power-aware interconnect optimization methodology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Information theoretic modeling and analysis for global interconnects with process variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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To achieve timing closure in a placed design, buffer insertion and driver sizing are two of the most effective transforms that can be applied. Since the driver-sizing solution and the buffer-insertion solution affect each other, suboptimal solutions may result if these techniques are applied sequentially instead of simultaneously. We show how to simply extend van Ginneken's buffer-insertion algorithm to simultaneously incorporate driver sizing and introduce the idea of a delay penalty to encapsulate the effect of driver sizing on the previous stage. The delay penalty can be precomputed efficiently via dynamic programming. Experimental results show that using driver sizing with a delay-penalty function obtains designs with superior timing and area characteristics.