Bus crosstalk fault-detection capabilities of error-detecting codes for on-line testing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Toward achieving energy efficiency in presence of deep submicron noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A practical methodology for early buffer and wire resource allocation
Proceedings of the 38th annual Design Automation Conference
Buffer block planning for interconnect planning and prediction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Feedback Control Theory
A survey of techniques for energy efficient on-chip communication
Proceedings of the 40th annual Design Automation Conference
Area and Energy-Efficient Crosstalk Avoidance Codes for On-Chip Buses
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Error-correction and crosstalk avoidance in DSM busses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Information Theoretic Capacity of Long On-chip Interconnects in the Presence of Crosstalk
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Optimal memoryless encoding for low power off-chip data buses
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
TIP-OPC: a new topological invariant paradigm for pixel based optical proximity correction
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Bus encoding for total power reduction using a leakage-aware buffer configuration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Coding for system-on-chip networks: a unified framework
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reliable communication under channel uncertainty
IEEE Transactions on Information Theory
Interconnect sizing and spacing with consideration of coupling capacitance
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Interconnect layout optimization under higher order RLC model for MCM designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A methodology for the simultaneous design of supply and signal networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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As the CMOS semiconductor technology enters nanometer regime, interconnect processes must be compatible with device roadmaps and meet manufacturing targets at the specified wafer size. The resulting ubiquitous process variations cause errors in data delivering through interconnects. This paper proposes an Information Theory based design method to accommodate process variations. Different from the traditional delay based design metric, the current approach uses achievable rate to relate interconnect designs directly to communication applications. More specifically, the data communication over a typical interconnect, a bus, subject to process variations ("uncertain" bus), is defined as a communication problem under uncertainty. A data rate, called the achievable rate, is computed for such a bus, which represents the lower bound on the maximal data rate attainable over the bus. When a data rate applied over the bus is smaller than the achievable data rate, a reliable communication can be guaranteed regardless of process variations, i.e., a bit error rate arbitrarily close to zero is achievable. A single communication strategy to combat the process variations is proposed whose code rate is equal to the computed achievable rate. The simulations show that the variations in the interconnect resistivity could have the most harmful effect regarding the achievable rate reduction. Also, the simulations illustrate the importance of taking into account bus parasitic parameters correlations when measuring the influence of the process variations on the achievable rates.