Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A graph based algorithm for optimal buffer insertion under accurate delay models
Proceedings of the conference on Design, automation and test in Europe
Maximizing throughput over parallel wire structures in the deep submicrometer regime
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power repeater insertion with both delay and slew rate constraints
Proceedings of the 43rd annual Design Automation Conference
Fast algorithms for slew constrained minimum cost buffering
Proceedings of the 43rd annual Design Automation Conference
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Power characteristics of inductive interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Recently Lillis, et al. presented an elegant dynamic programming approach to RC interconnect delay optimization through driver sizing, repeater insertion, and, wire sizing which employs the Elmore delay model for RC delay estimation and a crude repeater delay model. This approach, however, ignores an equally important aspect of interconnect optimization: transition time constraints at the sinks. More importantly, Elmore delay techniques because of their inherent inaccuracy are not suited to spec-based design which is directed towards synthesizing nets with user-specified delay/transition time requirements at the sinks. In this paper we present techniques for delay and transition time optimization for RC nets in the context of accurate moment-matching techniques for computing the RC delays and transition times, and an accurate driver/repeater delay model. The asymptotic increase in runtime over the Elmore delay model is O(q2) where q is the order of the moment-matching approximation. Experiments on industrial nets indicate that this increase in runtime is acceptable. Our algorithm yields delay and transition time estimates within 5% of circuit simulation results.