A graph based algorithm for optimal buffer insertion under accurate delay models
Proceedings of the conference on Design, automation and test in Europe
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
An architectural exploration of via patterned gate arrays
Proceedings of the 2003 international symposium on Physical design
Synthesis and placement flow for gain-based programmable regular fabrics
Proceedings of the 2003 international symposium on Physical design
A metal and via maskset programmable VLSI design methodology using PLAs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Buffering global interconnects in structured ASIC design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Via-configurable routing architectures and fast design mappability estimation for regular fabrics
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A lithography-friendly structured ASIC design approach
Proceedings of the 18th ACM Great Lakes symposium on VLSI
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The interconnection delay of pre-fabricated design style dominates circuit delay due to the heavily downstream capacitance. Buffer insertion is a widely used technique to split off a long wire into several buffered wire segments for circuit performance improvement. In this paper, we are motivated to investigate the buffer insertion issues in LUT-based structured ASIC design style. We design the layouts of two dedicated buffers and extract the technology dependent parameters for evaluations. After that, we propose a channel migration technique, which employs both intra-channel migration and inter-channel migration, to alleviate the sub-channel saturation problem. The experimental results demonstrate that dedicated buffers are essential for structured ASIC design style.