Temperature aware thread block scheduling in GPGPUs

  • Authors:
  • Rajib Nath;Raid Ayoub;Tajana Simunic Rosing

  • Affiliations:
  • University of California, San Diego;Strategic CAD Labs, Intel Corporation;University of California, San Diego

  • Venue:
  • Proceedings of the 50th Annual Design Automation Conference
  • Year:
  • 2013

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Abstract

In this paper, we present a first general purpose GPU thermal management design that consists of both hardware architecture and OS scheduler changes. Our techniques schedule thread blocks from multiple computational kernels in spatial, temporal, and spatio-temporal ways depending on the thermal state of the system. We can reduce the computation slowdown by 60% on average relative to the state of the art techniques while meeting the thermal constraints. We also extend our work to multi GPGPU cards and show improvements of 44% on average relative to existing technique.