Bounded-skew clock and Steiner routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On thermal effects in deep sub-micron VLSI interconnects
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
The Wiener--Askey Polynomial Chaos for Stochastic Differential Equations
SIAM Journal on Scientific Computing
Temperature-aware microarchitecture
Proceedings of the 30th annual international symposium on Computer architecture
Dynamic Thermal Management for High-Performance Microprocessors
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Reducing clock skew variability via cross links
Proceedings of the 41st annual Design Automation Conference
Microarchitectural power modeling techniques for deep sub-micron microprocessors
Proceedings of the 2004 international symposium on Low power electronics and design
TACO: temperature aware clock-tree optimization
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
An efficient method for terminal reduction of interconnect circuits considering delay variations
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Clock buffer and wire sizing using sequential programming
Proceedings of the 43rd annual Design Automation Conference
Pattern Recognition, Third Edition
Pattern Recognition, Third Edition
Minimal skew clock embedding considering time variant temperature gradient
Proceedings of the 2007 international symposium on Physical design
Dynamic thermal clock skew compensation using tunable delay buffers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Clock tree synthesis under aggressive buffer insertion
Proceedings of the 47th Design Automation Conference
Hotspot: acompact thermal modeling methodology for early-stage VLSI design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Uncertainty-aware dynamic power management in partially observable domains
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Thermal via allocation for 3-D ICs considering temporally and spatially variant thermal power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
iTEM: a temperature-dependent electromigration reliability diagnosis tool
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Temperature and supply Voltage aware performance and power modeling at microarchitecture level
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hermite Polynomial Based Interconnect Analysis in the Presence of Process Variations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An exact zero-skew clock routing algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Modern computing system applications or workloads can bring significant non-uniform temperature gradient on-chip, and hence can cause significant temperature uncertainty during clock-tree synthesis. Existing designs of clock-trees have to assume a given time-invariant worst-case temperature map but cannot deal with a set of temperature maps under a set of workloads. For robust clock-tree synthesis considering temperature uncertainty, this paper presents a new problem formulation: Stochastic PErturbation based Clock Optimization (SPECO). In SPECO algorithm, one nominal clock-tree is pre-synthesized with determined merging points. The impact from the stochastic temperature variation is modeled by perturbation (or small physical displacement) of merging points to offset the induced skews. Because the implementation cost is reduced but the design complexity is increased, the determination of optimal positions of perturbed merging points requires a computationally efficient algorithm. In this paper, one Non-Monte-Carlo (NMC) method is deployed to generate skew and skew variance by one-time analysis when a set of stochastic temperature maps is already provided. Moreover, one principal temperature-map analysis is developed to reduce the design complexity by clustering correlated merging points based on the subspace of the correlation matrix. As a result, the new merging points can be efficiently determined level by level with both skew and its variance reduced. The experimental results show that our SPECO algorithm can effectively reduce the clock-skew and its variance under a number of workloads with minimized wire-length overhead and computational cost.