On the bounded-skew clock and Steiner routing problems
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Predictive dynamic thermal management for multimedia applications
ICS '03 Proceedings of the 17th annual international conference on Supercomputing
An Algorithm for Zero-Skew Clock Tree Routing with Buffer Insertion
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Dynamic Thermal Management for High-Performance Microprocessors
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Hybrid Architectural Dynamic Thermal Management
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A yield improvement methodology using pre- and post-silicon statistical clock scheduling
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Statistical timing analysis driven post-silicon-tunable clock-tree synthesis
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
TACO: temperature aware clock-tree optimization
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Thermal resilient bounded-skew clock tree optimization methodology
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Dynamic thermal clock skew compensation using tunable delay buffers
Proceedings of the 2006 international symposium on Low power electronics and design
Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Dynamic thermal clock skew compensation using tunable delay buffers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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High performance VLSI designs require strict control over clock skew since skew directly impacts the cycle time calculation. For nano-meter CMOS designs, clock-skew and signal integrity are tremendously affected by process and temperature variations. A successful high performance VLSI design should not only aim to minimize the clock skew, but also control it while the chip is running. The issues rising out of temperature variations are particularly tough to tackle because of its dynamic, run-time nature. Although techniques for clock skew management/tuning due to temperature do exist in literature, they have mainly focused on how to solve skew issues, and have usually regarded the implementation of the thermal management scheme as a secondary problem. In this work we focus on the implementation issues involved in the implementation of a thermal management unit (TMU) relative to a skew management scheme based on the insertion of variable delay buffers (VDBs). We demonstrate the feasibility of the VDB-based methodology, and compare different implementation styles, showing that the most efficient TMU can be implemented with negligible overhead in various physical level metrics (0.67% in area, 0.62% in wire-length, 0.33% in power, and 0.37% in via-number).