Larger-than-vdd forward body bias in sub-0.5V nanoscale CMOS
Proceedings of the 2004 international symposium on Low power electronics and design
Temperature-aware circuit design using adaptive body biasing
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Thermally robust clocking schemes for 3D integrated circuits
Proceedings of the conference on Design, automation and test in Europe
Design of thermally robust clock trees using dynamically adaptive clock buffers
IEEE Transactions on Circuits and Systems Part I: Regular Papers
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The scaling trend of MOSFETs requires the supply and the threshold voltages to be reduced in future generations. Although the supply voltage is reduced, the total power dissipation and the static power of the chip are increased. Power dissipation is one of the limiting factors in achieving the highest performance of a chip. Therefore, new power reduction techniques are required. In this paper a new technique is introduced to reduce the power consumption. In this technique the supply voltage is changed dynamically as temperature changes. Using this technique, for 70nm devices the total power consumption of the chip can be reduced by 24% and the static power can be reduced by 40%. This reduction is achieved without any change in the worst-case delay.