Physical design methodologies for performance predictability and manufacturability
Proceedings of the 1st conference on Computing frontiers
Multilevel routing with antenna avoidance
Proceedings of the 2004 international symposium on Physical design
Temperature-aware global placement
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Interconnect and current density stress: an introduction to electromigration-aware design
Proceedings of the 2005 international workshop on System level interconnect prediction
introduction to electromigration-aware physical design
Proceedings of the 2006 international symposium on Physical design
Optimal jumper insertion for antenna avoidance under ratio upper-bound
Proceedings of the 43rd annual Design Automation Conference
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Advancing technology drives design technology andthus design automation (EDA). How to model interconnect, ho w to handle degradation of signal integrity and increasing power density are changing now, and have ledto integrating logic and layout synthesis. Agressive gatesizing to control timing has become part of any modernback-end. F rom 0:13µ and down, chips will be more susceptive to breakdown during fabrication (antenna effect)or to wear out over time (electromigration) and dealingwith these issues will require careful planning.More integration of fast and accurate analysis with acomplete design ow (chip planning, synthesis, placementand routing) will be needed, and still, advancing complexity will affect design and verification. Using hundredsof millions of devices effectively will be possible only byreusing pre-designed intellectual property (IP) effectivelyand by addressing system-level issues in EDA.In the long term only more radical changes willkeepus on Moore's track, changes that ultimately will haveus depart from the two+-dimensional confinement andlead to multiple active layers, and changes that will affectdeeply the face of EDA altogether.