FPGA routing architecture: segmentation and buffering to optimize speed and density
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Interconnect pipelining in a throughput-intensive FPGA architecture
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
Efficient circuit clustering for area and power reduction in FPGAs
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Placement rent exponent calculation methods, temporal behaviour and FPGA architecture evaluation
Proceedings of the 2003 international workshop on System-level interconnect prediction
A survey of fault tolerant methodologies for FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Prerouted FPGA cores for rapid system construction in a dynamic reconfigurable system
EURASIP Journal on Embedded Systems
FPGA Architecture: Survey and Challenges
Foundations and Trends in Electronic Design Automation
RAT: RC Amenability Test for Rapid Performance Prediction
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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We present an FPGA interconnect planning methodology based on the empirical measure known as Rent's Rule[8]. We show that allocation of wire segment lengths during the FPGA architecture planning phase can be improved by taking into account intercon驴nect complexities of the target circuits. We utilize previous work on netlist circuit fanout distribution[12] to estimate the FPGA seg驴mentation and employ a timing-driven placement and routing approach to get a minimized area-delay product. Our results indi驴cate that for logic clusters of various complexities, embedded in hierarchical FPGAs, our interconnect planning technique can improve circuit performance by an average of 10% and the area-delay product by an average of 29% over typical commercial FPGAs.