Structured design implementation: a strategy for implementing regular datapaths on FPGAs
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Quality of EDA CAD Tools: Definitions, Metrics and Directions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Power minimization algorithms for LUT-based FPGA technology mapping
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Hermes: LUT FPGA technology mapping algorithm for area minimization with optimum depth
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Congestion estimation and localization in fpgas:: a visual tool for interconnect prediction
Proceedings of the 2007 international workshop on System level interconnect prediction
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A two-phased approach for routability directed delay-optimal mapping of LUT based FPGAs is presented based on the results of stochastic routability analysis. First, delay-optimal mapping is performed which simultaneously minimizes area and delay. Then, the mapped circuits are restructured to alleviate the potential routing congestions. Experimental results indicate that the first phase creates designs which require 17% fewer levels and 40% fewer LUTs than MIS-pga (delay), 11% fewer levels and 37% fewer LUTs than FlowMap-r, and 5% fewer levels and 39% fewer LUTs than TechMap-D. The success of the second phase is confirmed by running a vendor's layout tool APR. It is observed that they are more routable and have less final delays than those produced by other mappers if they are placed and routed.