Chortle: a technology mapping program for lookup table-based field programmable gate arrays
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Symmetry detection and dynamic variable ordering of decision diagrams
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Simultaneous depth and area minimization in LUT-based FPGA mapping
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Logic decomposition during technology mapping
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
RASP: a general logic synthesis system for SRAM-based FPGAs
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Combinational logic synthesis for LUT based field programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA design
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Cut ranking and pruning: enabling a general and efficient FPGA mapping solution
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Area and search space control for technology mapping
Proceedings of the 37th Annual Design Automation Conference
DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization
IEEE Design & Test
Logic decomposition during technology mapping
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
BDD-based logic synthesis for LUT-based FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An efficient algorithm for finding the minimal-area FPGA technology mapping
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Improvements to technology mapping for LUT-based FPGAs
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
FPGA Design Automation: A Survey
Foundations and Trends in Electronic Design Automation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
On K-LUT based FPGA optimum delay and optimal area mapping
MACMESE'08 Proceedings of the 10th WSEAS international conference on Mathematical and computational methods in science and engineering
Reducing the pressure on routing resources of FPGAs with generic logic chains
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
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Conventional technology mapping algorithms for SRAM-based Field Programmable Gate Arrays (FPGAs) are normally carried out on a fixed logic decomposition of a circuit. The impact of logic decomposition on delay and area of the technology mapping solutions is not well understood. In this paper, we present an algorithm named SLDMap that performs delay-minimized technology mapping on a large set of decompositions and simultaneously controls the mapping area under delay constraints. Our study leads to two conclusions: (1) For depth minimization, the best algorithms in conventional flow (dmig + CutMap) produce satisfactory results with a short runtime, even with a fixed decomposition; (2) When all the structural decompositions of the 6-bounded Boolean network are explored, SLDMap consistently outperforms the state-of-the-art separate flow (dmig + CutMap) by 12% in depth and 10% in area on average; it also consistently outperforms the state-of-the-art combined approach dogma by 8% in depth and 6% in area on average.