Automatic Verification of In-Order Execution In Microprocessors with Fragmented Pipelines and Multicycle Functional Units

Authors:
P. Mishra;N. Dutt;A. Nicolau;H. Tomiyama
Affiliations:
Center for Embedded Computer Systems, University of California, Irvine, CA;Center for Embedded Computer Systems, University of California, Irvine, CA;Center for Embedded Computer Systems, University of California, Irvine, CA;Institute of Systems & Information Tech., Fukuoka 814-0001, Japan
Venue:
Proceedings of the conference on Design, automation and test in Europe
Year:
2002

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Abstract

As embedded systems continue to face increasingly higherperformance requirements, deeply pipelined processor ar-chitecturesare being employed to meet desired system per-formance.System architects critically need modeling tech-niquesthat allow exploration, evaluation, customizationand validation of different processor pipeline configurations,tuned for a specific application domain. We propose a novelFinite State Machine (FSM) based modeling of pipelinedprocessors and define a set of properties that can be used toverify the correctness of in-order execution in the presenceof fragmented pipelines and multicycle functional units. Ourapproach leverages the system architect's knowledge aboutthe behavior of the pipelined processor, through ArchitectureDescription Language (ADL) constructs, and thus allows apowerful top-down approach to pipeline verification. We ap-pliedthis methodology to the DLX processor to demonstratethe usefulness of our approach.