Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
DSN '00 Proceedings of the 2000 International Conference on Dependable Systems and Networks (formerly FTCS-30 and DCCA-8)
Fault Tolerance through Re-Execution in Multiscalar Architecture
DSN '00 Proceedings of the 2000 International Conference on Dependable Systems and Networks (formerly FTCS-30 and DCCA-8)
A Fault Tolerant Approach to Microprocessor Design
DSN '01 Proceedings of the 2001 International Conference on Dependable Systems and Networks (formerly: FTCS)
REESE: A Method of Soft Error Detection in Microprocessors
DSN '01 Proceedings of the 2001 International Conference on Dependable Systems and Networks (formerly: FTCS)
Evaluation of a 32-bit Microprocessor with Built-In Concurrent Error-Detection
FTCS '97 Proceedings of the 27th International Symposium on Fault-Tolerant Computing (FTCS '97)
AR-SMT: A Microarchitectural Approach to Fault Tolerance in Microprocessors
FTCS '99 Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
On-Line Integrity Monitoring of Microprocessor Control Logic
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Fault-Tolerant Systems in A Space Environment: The CRC ARGOS Project
Fault-Tolerant Systems in A Space Environment: The CRC ARGOS Project
Building dependable systems: how to keep up with complexity
FTCS'95 Proceedings of the Twenty-Fifth international conference on Fault-tolerant computing
Niche successes to ubiquitous invisibility: fault-tolerant computing past, present, and future
FTCS'95 Proceedings of the Twenty-Fifth international conference on Fault-tolerant computing
Control flow error checking with ISIS
ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
| Hi-index | 0.00 |
Control flow monitoring using a watchdog processor is a well-known technique to increase the dependability of a microprocessor system. Most approaches embed reference signatures for the watchdog processor into the processor instruction stream creating noticeable memory and performance overheads. A novel watchdog processor architecture using embedded signatures is presented that minimizes the memory overhead and nullifies performance penalty on the main processor without sacrificing error detection coverage or latency. This scheme is called Interleaved Signature Instruction Stream (ISIS) in order to reflect the fact that signatures and main instructions are two independent streams that co-exist in the system.