Evaluation of a 32-bit Microprocessor with Built-In Concurrent Error-Detection

  • Authors:
  • Jiri Gaisler

  • Affiliations:
  • -

  • Venue:
  • FTCS '97 Proceedings of the 27th International Symposium on Fault-Tolerant Computing (FTCS '97)
  • Year:
  • 1997

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Abstract

This paper describes the test results from heavy ion testing of ERC32, a 32-bit processing core with on-chip concurrent er-ror- detection. The parity based error-detection mechanisms succeeded in detecting more than 97.5% of all injected er-rors, significantly reducing the MTBFfor undetected SEU er-rors. Most errors occurred in registers, but some errors in combinational logic could also be observed. The cross-sec-tion for errors in combinational logic is however to small to have an influence on the overall error rate, The conclusion is therefore that parity based error-detection is well suited to detect SEU errors in VLSI devices for space applications.