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SAFECOMP '02 Proceedings of the 21st International Conference on Computer Safety, Reliability and Security
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DSN '01 Proceedings of the 2001 International Conference on Dependable Systems and Networks (formerly: FTCS)
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Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems
Partitioning techniques for partially protected caches in resource-constrained embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On the effects of errors during boot
LADC'05 Proceedings of the Second Latin-American conference on Dependable Computing
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This paper describes the test results from heavy ion testing of ERC32, a 32-bit processing core with on-chip concurrent er-ror- detection. The parity based error-detection mechanisms succeeded in detecting more than 97.5% of all injected er-rors, significantly reducing the MTBFfor undetected SEU er-rors. Most errors occurred in registers, but some errors in combinational logic could also be observed. The cross-sec-tion for errors in combinational logic is however to small to have an influence on the overall error rate, The conclusion is therefore that parity based error-detection is well suited to detect SEU errors in VLSI devices for space applications.