Reducing pin and area overhead in fault-tolerant FPGA-based designs

Authors:
Fernanda Lima;Luigi Carro;Ricardo Reis
Affiliations:
Universidade Federal do Rio Grande do Sul, Porto Alegre, RS, Brazil;Universidade Federal do Rio Grande do Sul, Porto Alegre, RS, Brazil;Universidade Federal do Rio Grande do Sul, Porto Alegre, RS, Brazil
Venue:
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Year:
2003

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Abstract

This paper proposes a new high-level technique for designing fault tolerant systems in SRAM-based FPGAs, without modifications in the FPGA architecture. Traditionally, TMR has been successfully applied in FPGAs to mitigate transient faults, which are likely to occur in space applications. However, TMR comes with high area and power dissipation penalties. The proposed technique was specifically developed for FPGAs to cope with transient faults in the user combinational and sequential logic, while also reducing pin count, area and power dissipation. The methodology was validated by fault injection experiments in an emulation board. We present some fault coverage results and a comparison with the TMR approach.