Design of a soft-error robust microprocessor

Authors:
Rodrigo Possamai Bastos;Fernanda Lima Kastensmidt;Ricardo Reis
Affiliations:
Universidade Federal do Rio Grande do Sul (UFRGS), Instituto de Informática, PGMICRO PO Box 15064, 91501-970, Porto Alegre, RS, Brazil;Universidade Federal do Rio Grande do Sul (UFRGS), Instituto de Informática, PGMICRO PO Box 15064, 91501-970, Porto Alegre, RS, Brazil;Universidade Federal do Rio Grande do Sul (UFRGS), Instituto de Informática, PGMICRO PO Box 15064, 91501-970, Porto Alegre, RS, Brazil
Venue:
Microelectronics Journal
Year:
2009

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Abstract

The costs to protect a commercial microprocessor against soft errors are discussed in this work. Based on hardware and time redundancies, a protection scheme was designed at RT level to mitigate transient faults on combinational and memory circuits. A fault-tolerant IC version of a mass-produced 8-bit microprocessor is protected by the scheme. Design issues and results in area, performance and power are presented comparing the robust microprocessor with its non-protected version. The costs by flip-flop are also discussed permitting to estimate the overheads in area for any architecture. Furthermore, the RT-level protection scheme is compared with an electrical-level scheme based on a non-standard gate.