Design & analysis of fault tolerant digital systems
Design & analysis of fault tolerant digital systems
Modeling the cosmic-ray-induced soft-error rate in integrated circuits: an overview
IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors
Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Going beyond TMR for protection against multiple faults
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Multiple Transient Faults in Logic: An Issue for Next Generation ICs
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Self-Stabilizing Microprocessor: Analyzing and Overcoming Soft Errors
IEEE Transactions on Computers
SET Fault Tolerant Combinational Circuits Based on Majority Logic
DFT '06 Proceedings of the 21st IEEE International Symposium on on Defect and Fault-Tolerance in VLSI Systems
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This work proposes the use of analog majority gates to implement combinational circuits that are intrinsically tolerant to transient faults. A new type of voter circuit, that uses some knowledge from the analog design arena is proposed, together with a new mapping approach to implement circuits given their input/output table. This new mapping approach is shown to compare favorably against a classic mapping. The implementation and validation of an adder circuit, using conventional triple modular redundancy (TMR), the classic mapping, and the proposed solution are analyzed, in order to confirm that the shown technique is indeed fault tolerant, and has advantages in terms of area and performance when compared to TMR. Finally, implementations of a subset of the ISCAS 85 benchmark circuits using TMR with the analog voter and the proposed approach are compared and the results analyzed.