Using majority logic to cope with long duration transient faults

Authors:
Lorenzo Petroli;Carlos A. Lisboa;Fernanda L. Kastensmidt;Luigi Carro
Affiliations:
Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil;Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil;Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil;Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil
Venue:
Proceedings of the 20th annual conference on Integrated circuits and systems design
Year:
2007

Citing 6
Cited 0

Design & analysis of fault tolerant digital systems

Design & analysis of fault tolerant digital systems
Cost reduction and evaluation of temporary faults detecting technique

DATE '00 Proceedings of the conference on Design, automation and test in Europe
Going beyond TMR for protection against multiple faults

SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Multiple Transient Faults in Logic: An Issue for Next Generation ICs

DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
SET Fault Tolerant Combinational Circuits Based on Majority Logic

DFT '06 Proceedings of the 21st IEEE International Symposium on on Defect and Fault-Tolerance in VLSI Systems
System Level Approaches for Mitigation of Long Duration Transient Faults in Future Technologies

ETS '07 Proceedings of the 12th IEEE European Test Symposium

Quantified Score

Hi-index	0.01

Visualization

Abstract

This work proposes the use of analog majority gates to implement combinational circuits that are intrinsically tolerant to long duration transient faults predicted for future technologies. The reasoning behind that prediction is explained, a new type of voter circuit, that uses some knowledge from the analog design arena, to implement majority gates is reviewed, and a new mapping approach to implement circuits using networks of majority gates is proposed. The implementation and validation of an adder circuit, using TMR with an analog voter and the proposed solution are analyzed, in order to confirm that the technique is indeed fault tolerant, and has advantages in terms of area and performance when compared to TMR.