Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
DRG-cache: a data retention gated-ground cache for low power
Proceedings of the 39th annual Design Automation Conference
Level conversion for dual-supply systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Clocking and clocked storage elements in a multi-gigahertz environment
IBM Journal of Research and Development
Dual-edge triggered storage elements and clocking strategy for low-power systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Impact of Gate-Length Biasing on Threshold-Voltage Selection
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Low-power clock branch sharing double-edge triggered flip-flop
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This work presents a low-power dual-edge triggered static scanable flip-flop that uses reduced swing-clock and -data to manage dynamic power. The circuit employs clock- and power-gating during idle mode to eliminate dynamic power and reduce static power, while retaining circuit’s state. The static structure of the circuit makes it feasible to be employed in variable frequency power control designs. HSPICE post-layout simulation conducted for 90nm CMOS technology showed that in terms of power-delay product, device count, and leakage power the proposed design is comparable to other high performance static flip-flops.