Clocking Schemes for High-Speed Digital Systems
IEEE Transactions on Computers
A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor
Digital Technical Journal
Analysis and design of low-energy flip-flops
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Digital System Clocking: High-Performance and Low-Power Aspects
Digital System Clocking: High-Performance and Low-Power Aspects
Analysis and design of voltage-controlled oscillator based analog-to-digital converter
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Power-efficient explicit-pulsed dual-edge triggered sense-amplifier flip-flops
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Glitch-free NAND-based digitally controlled delay-lines
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A new sense-amplifier-based flip-flop is presented. The output latch of the proposed circuit can be considered as an hybrid solution between the standard NAND-based set/reset latch and the NC-2 MOS approach. The proposed flip-flop provides ratioless design, reduced short-circuit power dissipation, and glitch-free operation. The simulation results, obtained for a 0.25-µm technology, show improvements in the clock-to-output delay and the power dissipation with respect to the recently proposed high-speed flip-flops. The new circuit has been successfully employed in a high-speed direct digital frequency synthesizer chip, highlighting the effectiveness of the proposed flip-flop in high-speed standard cell-based applications.