ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
HPCA '02 Proceedings of the 8th International Symposium on High-Performance Computer Architecture
IBM Journal of Research and Development
Statistical Timing Analysis: From Basic Principles to State of the Art
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This work investigates the interrelation of performance and robustness against variability in industrial microprocessor designs. A novel analysis technique for variation-sensitive hardware and two figures of merit to quantify the robustness of a design against variations are proposed. Together with a multi-stage STA this enables an efficient application of low-VT cell insertion and pulsed latch design to compensate for within-die delay variations. For the same speed margin of 5% on design level, a pulsed latch design of an ARM926 microprocessor shows a 2.5x higher robustness compared to a MS-FF design with selective low-VT cell insertion.