Digital systems engineering
A physical model for the transient response of capacitively loaded distributed rlc interconnects
Proceedings of the 39th annual Design Automation Conference
Digital System Clocking: High-Performance and Low-Power Aspects
Digital System Clocking: High-Performance and Low-Power Aspects
Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Estimating reliability and throughput of source-synchronous wave-pipelined interconnect
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
High speed interconnect data dependent jitter analysis
Microelectronics Journal
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Timing jitter in long on-chip interconnects has become an increasingly important issue in signal integrity and timing violations. In this paper, we focus on cycle-to-cycle jitter induced by repeater power supply noise in bothpoint-to-point and branched RC and RLC interconnects in 70nm CMOS. We develop an analytical expression for jitter based on propagation delay variation that accurately predicts HSPICE simulation results. We show the difference in impact between RC and RLC wire models on jitter (up to 64%). We also show a method for jitter-optimal repeater insertion which differs from conventional delay optimal insertion methods, resulting in larger repeaters. Finally, we introduce methods which can decrease timing violations in branched global interconnects by adjusting repeater size and tuning the phase of the power supply noise.