Effects of inductance on the propagation delay and repeater insertion in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 38th annual Design Automation Conference
Modeling of coplanar waveguide for buffered clock tree
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Jitter in Deep Sub-Micron Interconnect
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Current-sensing and repeater hybrid circuit technique for on-chip interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Differential current-sensing for on-chip interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Rapid approximation of the transient response of high-speed global interconnects is needed to estimate the time delay, crosstalk, and overshoot in a GSI multilevel wiring network. This paper outlines a rigorous and physical solution for transients in a capacitively-loaded distributed rlc interconnect using a convergent series of modified Bessel functions. Compact models for time delay and repeater insertion are derived. The single-line model is extended to evaluate crosstalk in two-coupled lines. These solutions are validated by HSPICE simulation, and have potential applications to rapid rlc timing analysis, global wire sizing and repeater insertion, signal integrity estimation, and reliability modeling (e.g. voltage overshoot and high current density concerns).